1. Field of the Invention
The subject invention relates to a graphics data processing system which produces a visual graphics display and more specifically to a memory arrangement for such a system.
2. Description of Related Art
In the prior art, computer systems use bit-mapped video displays to produce an image from representative data produced and stored within the system. A bit-mapped display uses a bit-mapped memory that stores at least one binary digit for each pixel of the display device. Additional digits may be stored for each pixel. Such additional digits stored for each pixel provide the capability of the system to render complex images on the video display. The use of a bit-mapped memory also allows the computer system to readily generate and modify the image to be displayed.
The display device may be of the raster-scan type wherein an electron beam carrying variations, representing image data variations, traces horizontal lines across the display screen to create the desired visual image. At the end of each horizontal line trace, the electron beam with information blacked out retraces to the origin side of the display. From there the electron beam commences another raster scan vertically off-set from the prior raster scan. By continuing this procedure, the desired image is reproduced on the display screen.
In order to increase the resolution of the displayed image, more pixels must be used in the image. The increased number of pixels must be presented to the display screen in the same amount of time because the raster operates at a fixed rate sweeping across the display screen.
Multiport random access memories have been developed for providing both high speed data output to the video display and rapid accessibility of memory contents to the data processor. The memories accomplish this by having a first port for random access to and update of the memory contents by the data processor and a second port for serial output of the memory contents to the video display. The first and second ports are asynchronous with respect to each other. Random access to the memory contents of the memory is available during data output operations to the video display.
A single memory device may include a memory plane having a plurality (such as four) of memory arrays arranged so that each array has each of its storage cells located at a column and row address which is identical with the row and column address of a storage cell in each of the other memory arrays. When data is written into any storage location, a binary digit is written simultaneously into a cell having the same address location in each of the memory arrays.
The multiple bits of information representing a single pixel may provide intensity or color information for the desired image to be displayed. Often a large number of memory addresses store identical information for the desired display. When this identical information is to be stored or refreshed in the memory plane, a block write operation may be used to accomplish the operation faster. In the block write operation, identical information is written simultaneously into a plurality of adjacent address locations. Thus several (for instance four) adjacent storage locations are written simultaneously into each memory array of the memory plane. Thus information is written simultaneously into four storage cells of each of four memory arrays. Only one random access operation is used to accomplish the block write operation. A resulting four-to-one writing speed-up is achieved.
Because of demands for increased memory capacity for data processing systems using a video display, larger video random access memories are being developed. One way to increase the capacity is to multiply the number of memory arrays in the memory plane, e.g., double from four arrays to eight arrays per memory plane or quadruple from four arrays to sixteen arrays per memory plane.
Doubling or quadrupling the number of memory arrays per memory plane creates problems for a data processing system designed for block writing into the memory device.